I have blogged before on how to import Xilinx ISE projects in Sigasi before. In this blog post I show how you can import an existing Vivado project into Sigasi.
If you have a Vivado project which uses one or more IP cores, the project becomes complex quickly. Vivado generates different sources for Simulation and Synthesis. And although VHDL has elegant support for this –entities can have multiple architectures–, Vivado generates duplicate entities instead.